Once a newly designed integrated circuit (IC) has been formed on a silicon substrate, the IC must be thoroughly tested to be sure that the circuit performs as intended. Any portion of the IC which does not function properly must be identified so that it can be fixed by modifying the design of the IC. This process of testing an IC to identify problems with its design is known as debugging. After debugging the IC and correcting any problems with its design, the final, fully functional IC designs are used to mass produce the IC's in a manufacturing environment for consumer use.
During the debugging process, it is often necessary to probe certain electrical interconnect lines in order to obtain important electrical data from the IC, such as, for example, voltage levels, timing information, current levels, and thermal information. A typical IC device contains multiple layers of metal interconnects. However, the metal interconnects in the first metal layer of an IC device generally carry the most valuable electrical data for debugging purposes. Metal interconnect lines in the first metal layer reside closest to the silicon substrate and are usually directly coupled to important components of the IC device such as transistors, resistors, and capacitors. It is the electrical data received, manipulated, and transmitted by these components which a designer is most interested in analyzing during the debugging process.
FIG. 1a illustrates a surface view of the top side of an IC device. Metal interconnect lines and components of IC device 11 have been formed on an underlying silicon substrate. The side of the silicon substrate upon which the IC is formed shall herein be referred to as the top side of the silicon substrate. As illustrated in FIG. 1a, bond pads 13 are located along the periphery of IC device 11. In the center of IC device 11 is the active region 12 containing the majority of the high density, active circuitry of IC device 11. It is within active region 12 that most probing takes place during the debugging process. While probing the interconnect lines in active region 12, it is necessary to externally supply the proper voltage signals to bond pads 13 to activate the circuitry within the active region. These voltage signals are supplied to bond pads 13 through a package to which IC device 11 is affixed.
FIG. 1b illustrates a cross-section of IC device 11 after being packaged. After IC device 11 is affixed to package substrate 15, individual bond wires 14 are used to electrically couple each bond pad 13 to a corresponding pad on package substrate 15. Each corresponding pad on package substrate 15 is then individually coupled to an external pin 16. The packaged IC device of FIG. 1b may then be placed within a socket in order to electrically couple external pins 16 to drivers which supply the necessary voltage signals to activate IC device 11. As illustrated in FIG. 1b, IC device 11 is mounted to package substrate 15 with its top side facing away from package substrate 15. In this manner, once IC device 11 is activated through package pins 16, the internal, active region 12 may be accessed and probed since neither bond pads 13, package substrate 15, nor bond wires 14 obscure access to this region of IC device 11.
There are several problems with the design of IC device 11 and its method of packaging. One problem stems from the fact that as the density and complexity of IC device 11 increases, so must the number of bond pads required to control the functions of IC device 11. However, there is only a finite number of bond pads 13 which can fit along the periphery of IC device 11. One way to fit more bond pads along the periphery of the IC device is to increase the overall size of the device thereby increasing its peripheral area. Unfortunately, this also significantly increases the IC manufacturing costs. Another problem with IC device 11 is that the active circuitry within region 12 must be routed to the peripheral region of IC device 11 in order to be electrically coupled to bond pads 13. By routing these interconnect lines over this relatively long distance across the IC, the increased resistive, capacitive, and inductive effects of these lengthy interconnect lines result in speed reduction of the IC device. In addition, the inductance of the bond wires 14 will also severely limit the high frequency operation of IC devices in these packages.
Techniques have been employed to overcome these and other limitations of the design and packaging of IC device 11. FIG. 2a illustrates a top side view of IC device 20. As illustrated in FIG. 2a, bond pads 21 have been formed along the top of the entire IC device so that the bond pads now reside directly over the active circuitry region of IC device 20. By forming bond pads in both the center and periphery of IC device 20, more bond pads can be placed across the surface of the device than can be placed only within the peripheral region. In addition, active circuitry which underlies bond pads 21 of IC device 20 can be directly coupled to its nearest bond pad using relatively short interconnect lines. This minimizes the resistive, capacitive, and inductive effects associated with routing interconnect lines over long distances, improving speed performance.
FIG. 2b is an illustration of a cross-section of IC device 20 after being mounted to a package substrate 22. In order to mount IC device 20 to package substrate 22, solder balls 24 are placed on each of bond pads 21 to electrically couple each bond pad 21 to its corresponding pad on package substrate 22. Each corresponding pad on package substrate 22 is, in turn, coupled to an external pin 23. Note that IC device 20 is mounted to package substrate 22 with its top side facing towards the package substrate. In contrast, IC device 11 of FIG. 1b is mounted to package substrate 15 with its top side facing away from the package substrate. In other words, in comparison to the method used to mount IC device 11 to its package substrate 15, IC device 20 is "flipped." For this reason, the design of IC device 20 illustrated in FIG. 2a and it's subsequent packaging method illustrated in FIG. 2b is referred to as flip-chip technology. The technology is also known as controlled collapse chip connection (C4), named after the package mounting technique of using solder to replace bond wires.
As can be seen in FIGS. 2a and 2b, the top of IC device 20 is obscured by bond pads 21, solder balls 24, and package substrate 22. Such is the case for all IC devices packaged using C4 technology. Therefore, it is impossible to probe the circuitry of IC device 20 in the conventional manner described above since the circuitry of IC device 20 cannot be accessed from its top side.
Alternative techniques have been employed to permit access to the interconnect lines on top of IC device 20 so that these lines can be probed. One technique involves redesigning the C4 IC device so that it can be packaged in a conventional wire bond package. The redesigned wire bond packaged IC device may then be probed from the top of the silicon substrate in a more conventional manner. Unfortunately, the C4 IC device redesigned for wire bond packaging functions differently in a wire bond package than it would in its intended C4 package. As a result, the debugging process is hindered by the fact that electrical data collected during probing of the redesigned C4 IC device may not accurately reflect actual performance of the device when packaged in its native, C4 package environment.
A method is needed whereby a C4 IC device can be probed while in its native C4 package environment. This would allow electrical data to be collected from the IC device which reflects the true performance of the device as it was intended to operate.